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<pre>Array ( [var] => cut_url ) </pre> Resume for Gaurav B. for Engineer / Computer Hardware in Raleigh, North Carolina. Search More Resumes for Engineer on Resumark.com #EIA847A28
 

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Resume for Gaurav B. for Engineer / Computer Hardware in Raleigh, North Carolina




Occupation: Engineer Industry: Computer Hardware
Country: United States City: Raleigh
State: North Carolina ZIP: 27606



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Gaurav.R.B. Champion Court, Avent Ferry Road,Raleigh ,NC | | Objective Seeking a full time position in the field of ASIC Design and Verification where I can contribute to the organization through dedication, innovation and excellence. Education North Carolina State University Raleigh, NC M.S in Computer Engineering GPA ­ . Mumbai University ­ Mumbai, India B.E in Electronics and Telecommunication Engineering Aggregate ­ % Graduating December Professional Experience Protochips, Inc. Process Technician January Present Working in a IC fabrication environment with various tools and processes in etching, metrology and lithography. Coursework VLSI Design ASIC Design FALL Digital Signal Processing Computer Design and Technology Independent Studies on D Interconnects Advanced Microarchitecture IC Fabrication and Technology Digital Electronics Wireless Communication Systems ASIC Verification Technical Skills and Abilities Operating Systems Windows, Linux. Programming Languages Verilog , C, C++ , MATLAB, VHDL. Design Tools Cadence Virtuoso, Cadence Cscope, Synopsys HSpice, Synopsys Sentaurus P, Mentor ModelSim, Synopsys Designware. Projects Packet Forwarding Engine Designed part of networking ASIC performing routing operation while looking up trie structure stored in onchip SRAM and destination ports in offchip DRAM. Optimized the design for best performance per unit area using several techniques. Used Mentor ModelSim for simulation and Synopsys Design Compiler for Synthesis. Ranked in a class of on the basis of clean design and performance. High Speed Flip Flop Design Designed a high speed Hybrid Latch flip flopHLFF using the nm NCSU PDK able to operate at GHz. Optimized the design for power consumption which was recorded to be . uW. Scored / on performance points hinting best in class performance. Used Synopsys HSpice and Cadence CosmoScope for design and analysis. High Speed Transmitter Design Designed a differential multistage driver circuit with an equalization filter for a given Independent interconnect model with nm NCSU PDK. Minimized the power consumption while maintaining a Bit Error Rate BER of Analyzed the design tradeoffs for power and speed. Study on Investigation of power and performance of interconnects in .D and D IC&;s Devised an interconnect model for an interposer as a part of project specification of a Doctoral Course. Devised an interconnect model for nm Through Silicon ViaTSV. Worked with ASU Predictive Kit. Evaluated several interconnect models with respect to power and performance. Stage Router Pipeline Designed a full custom schematic and layout of router pipeline and verified with input vectors. Optimized the design for minimum Energy delay squared productED P. Verified functionality using Cadence Virtuoso, HSpice and CScope. Validated the design through DRC, LVS and LFD checks. Cache and Memory Hierarchy Design Developed a C++ code to simulate a two level memory hierarchy with configurable replacement and write policies. Extended the simulator to support a victim cache with the two level hierarchy. Analyzed the performance of the cache structure for various input trace files. Branch Prediction Simulator Developed a C++ code for simulating three branch predictor algorithms. Optimized the predictor design to minimize the misprediction rate and cost for specific input traces. Dynamic Instruction Scheduling Simulator Developed a C++ code to implement Tomasulo Algorithm for outof order execution of instructions. Discussed the variation of IPC with Scheduling Queue Size for specific trace files. MOSFET Fabrication Simulation Designed a nm MOSFET with recessed source drain junctions, according to the ITRS specifications and simulated in Synopsys Sentaurus Process tool. FPGA Implementation of a Single Channel HDLC Layer Protocol Transmitter Using VHDL Designed and Synthesized a VHDL code for HDLC transmitter on Xilinx Spartan E FPGA. Leadership and Interests . Served as Chairman Of Institute Of Electronics and Telecommunication Engineers IETE Student Council for . . . . . Worked as Treasurer for the Associate Student Council for . Organized a Robotics Workshop for freshmen at the Undergraduate level in . Volunteered with undergraduate college managed Orphanage in various activities. Like traveling to new places, meeting new people, learning about different cultures and backgrounds.

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