Array
(
    [var] => cut_url
)
<pre>Array ( [var] => cut_url ) </pre> Resume for Nisha D. for Engineer / Computer Hardware in San Jose, California. Search More Resumes for Engineer on Resumark.com #YAK883ORD
 

Search Resumes

Post Jobs
 


Job Seekers:
Post Your Resume


 

Resume for Nisha D. for Engineer / Computer Hardware in San Jose, California




Occupation: Engineer Industry: Computer Hardware
Country: United States City: San Jose
State: California ZIP: 95112



View Complete Resume   Download Resume [
Array
(
    [name] => cut_url
)
TXT]
Share Share


< Back to search results Preview: For the complete resume and contact info please download it.

Array
(
    [var] => content
    [type] => preview
)
Array
(
    [var] => cut_url
)
, E San Fernando, NISHA D. CONTACT San Jose, CA EDUCATION SJSU, University of California Pursuing Masters of Science EEVLSI University of Mumbai, India MAY Bachelor of Engineering Electronics University of S.N.D.T., India MAY Diploma of Engineering Electronics SKILLS Platform: Linux, Windows /Xp/Vista, MSDOS Programming Language: Verilog HDL, System Verilog, Assembly Language x/, C Scripting: Perl, Cshell, Protocol: AMBA AHB, APB, AXI, SAS, SATA, PCI, Ethernet, IC, Tools: EDA: VCS, Questa, VSIM, Verdi, Xgig Trace View URG; Linting: Spyglass for lint and structural check, Tanner: TSPICE Version Control System: CVS, SVN WORK EXPERIENCE * LSI R&D India Pvt. Ltd., Pune, India JULY JULY Design Verification Engineer I [RAID STORAGE DIVISION] Front end Digital Design, SAS, SATA * Coowner for SAS/SATA Expander&;s one of the crucial block which makes expander self sufficient to handle traffic between HBA and drive and works irrespective of drive speed being bottleneck in the system. * Bug fixing, Debugging on FPGA Emulation Platform * Manual ECO development in netlist as well LEC automated ECO flow experience * Written its Engineering Design Specification, Technical documents, made block Lint clean, did code coverage analysis. * CoOwner of onchip memory controller IP for the SAS/SATA Expander. * Implemented AMBA AXI to AXI/AHB bus matrix specific to the SAS/SATA Expander next gen chip done by LSI. * Published the paper on "Using Distributed HDL Simulation for accelerated SOC/IP development" and presented it in LSI Annual Technical Conference . * Did basic verification IC masterslave one of the block of SAS/SATA Expander Chip. * LSI R&D India Pvt. Ltd., Pune, India SEP JULY VLSI Project Trainee [RAID STORAGE DIVISION] Jr. Verification Engineer * Designed and verification of Router as my first warm up activity. Implemented its Micro and Macro Architecture, design flow and guidelines. Built its verification environment based on System Verilog. * Worked as a junior verification engineer on DMA Engine and RAID Accelerator. Wrote and simulated some testcases * Analyzed code coverage using VCS as EDA tool for one of the block in DMA Engine and RAID Accelerator. Made script for URG Unified Coverage Report for generating coverage reports * Worked on one project based on an observable fact Distributed HDL Simulation, made it production based so that can be used in any of the projects. For the same worked on areas like socket programming, server implementation, PERL scripting, PLI and DPI programming. * Wipro Technologies, Bangalore , India SEP SEP VLSI Project Engineer Design Engineer * Attended training on Basic digital design Concepts and synthesizable HDL, VLSI design and verification guidelines and methodology, Static Timing Analysis, Code coverage analysis. * ASIC Designing and verification of stopwatch as a internal project of Wipro * IP implementation of AHB based SOC for the same understood concepts AMBA and AHB, APB, and AXI Protocol. * Transasia BioMedical, Mumbai, R&D Department [R & D INTERN] DEC JUN * Worked on Biomedical product verification on C kile based platform. * Wrote small program for their CPLD based product blood tester * Aplab Pvt. Ltd., Mumbai, R&D Department [R & D INTERN] JUNE DEC * Worked on function generators and Digital Multimeters * Learnt microcontroller programming in Assembly language. * DELTA Control Engineering Corporation, Mumbai [Summer Trainee] MAY JUN + Worked in Testing and Calibration Department for signal generator, and Multimeters ACADEMIC PROJECTS * B.E. Project: MODELLING AND SIMULATION OF SOI DEVICES JULY MAY + Understood what is SOI devices, it&;s various models like BSI model, threshold voltage model, Subthreshold current model, mobility and strong inversion current model. + Simulated SOI model in TSPICE for o Basic NMOS and PMOS device, o AND, OR,NOR,NAND,AND gates, o SRAM, Manchester, o Carry Chain * Mini Project: IR based Home Automation Prototype JULY This system uses IR to control the home appliances through remote control. * Mini Project: Solar Night Flasher JULY This flasher has rechargeable Ni Battery which gets charged from solar energy through solar cell. * Mini Project: Number Guessing Game JULY This game will guess the number by converting it into BCD. It is basically used in entertainment industry. * Diploma Project : Robotic Arm JUNE DEC Developed electromechanical Robotic Arm, which will function as per instruction given by keys. In LEARN mode, it will store the performed task in RAM. In PLAY mode, it can continue doing the same task till power is not turned off. RELATED TRAININGS * SAS./SATA. Protocol JAN * Basic Verilog and Digital design Concepts and synthesizable HDL, SEP JAN * VLSI design and verification guidelines and methodology, Code coverage analysis * Static Timing Analysis, Spyglass Linting Tool EXTRA CURUCULAR ACTIVITIES * Volunteered People&;s Fiesta TMT Level Group Event Wipro Technologies * participated and won rd prize in inter college project competition named PRAYAS in Diploma College * Organized and volunteered seminars, Project competition, inter college festivals AWARDS & ACHIEVEMENTS * State level merit holder at Diploma level * School level merit holder at S.S.C. level in School * Awarded scholarship from JRD TATA, Modh Vanik gujarati samaj, rotary club of Mumbai in the second year of Bachelor&;s of Engineering. LIST OF PUBLICATIONS * Nisha D., Prakash Bodhak, Aditya Pagonda "Using Distributed HDL Simulation for accelerated SOC/IP development", LSI Annual Technical Conference on th Jan at LSI R&D India Pvt. Ltd., Bangalore. * Nisha D., Laxman Pai, Rajesh Bhole, Kiran Purabia and S. S. Rathod "Design of Digital and Analog Circuits Using SOI Technology for Nano Scaled Devices", International conference on Nano and Microelectronics ICONAME on rd th Jan. at Pondicherry Engineering College, Pondicherry. * Nisha D., Laxman Pai, Rajesh Bhole, Kiran Purabia and S. S. Rathod "Simulation of Various SOI Models at Nanometer Technology", SPITIEEE Colloquium and First International conference on th th Feb. at Sardar Patel Institute of Technology, Mumbai.

Cancel
Not Enough Credits
Sorry, but you don't have enough credits to download this resume.

Purchase more credits
Not Available
Sorry but this resume is not available for download. Please choose another!

Close
Confirm Download

Would you like to download  for 1 credit?

You have  credits left.

Yes No 

Don't ask me again
Confirm View Complete Resume

Would you like to view  for 1 credit?

You have  credits left.

Yes No 

Don't ask me again