Array
(
    [var] => cut_url
)
<pre>Array ( [var] => cut_url ) </pre> Resume for Mei Myen C. for Engineer / Computer Software in Petaling Jaya, Malaysia. Search More Resumes for Engineer on Resumark.com #COU8CRBEW
 

Search Resumes

Post Jobs
 


Job Seekers:
Post Your Resume


 

Resume for Mei Myen C. for Engineer / Computer Software in Petaling Jaya, Malaysia




Occupation: Engineer Industry: Computer Software
Country: Malaysia City: Petaling Jaya
State: Selangor ZIP: 47400



View Complete Resume   Download Resume [
Array
(
    [name] => cut_url
)
MS WORD]
Share Share


< Back to search results Preview: For the complete resume and contact info please download it.

Array
(
    [var] => content
    [type] => preview
)
Array
(
    [var] => cut_url
)

CURRICULUM VITAE 

Full Name   :  C. Mei Myen, Joyce

IC No.   : 

Address  :  No , Jalan SS/, Damansara Jaya

Telephone No.   :  +

Email   :

Gender   :  Female

Age   : 

Date of Birth  :  rd July,  

Place of Birth  :  Sabah

Marital Status  :  Married

Race   :  C.ese 

Nationality  :  Malaysia

Visas   :  B, L Visas US

Health   :  Good condition

Height and Weight  :  cm, kg 

Languages Spoken Proficiency:  English Best= Worst=

     Malay   Best= Worst=

     Mandarin Best= Worst=

Languages Written Proficiency:  English   Best= Worst=

    Malay     Best= Worst=

          Mandarin Best= Worst= 

WORKING EXPERIENCE 

Company : IBM Malaysia Sdn Bhd /Current

Position: Software Engineer

Department: Malaysia Development Lab MDL 

Job Description:

Key responsibilities are to develop, modify & execute software test plans; assist with analysis & development of test standards and procedures; maintain documentation of test results; analyze test results to ensure existing functionality and recommend corrective action; consult with development engineers in problem resolution; provide feedback in preparation of technical appraisals of programming languages, systems and computation software; ensure quality computer integration into the overall functions of scientific computation, data acquisition & processing. 

Achievement:

  • SME expert for OMNIbus jAuto automation.
  • Leading L OMNIbus jAuto automation in infrastructure setup, test case definition and java coding. Familiar with development tool Rational Application Developer and Eclipse. Coded ~ java test cases per month.
  • Successfully setup st local jAuto infrastructure in MDL, which consists of Rational Clear Case, Rational Team Concert RTC, Rational Applications Developer RAD installation and STAF/STAX framework.
  • Created user documentation on infrastructure setup, e.g download and installation steps and leverage the knowledge to team members. Created RQM Test Case Writing Guideline via Automation Strategy to help automation testers avoid common mistakes and improves the automated testing process.
  • Successful transition of L Omnibus testing activities from India within month of project overlapping.
  • Pioneered first OMNIbus Fixpack release in MDL OMNIbus ... and ....
  • Testing ownership of L OMNIbus ., .., .., . and ... Release ownership of IBM software to customers through DCF and FixCentral.
  • Experienced in Test Director, Rational ClearQuest, ClearCase and Rational Quality Manager RQM.
  • Patent group representative for Software Quality Assurance. Active involvement in discussion, presentation and idea submission.
  • Rated + above average contributor within ½ year of project engagement in IBM and for years consecutively.
  •  

    Company : Freescale Semiconductor //

    Position: Senior Test Development Engineer

    Department: Networking & Multimedia Group 

    Job Description:

    Plan and execute projects to improve cost, yield, quality, performance, and productivity of products in portfolio. Evaluate functionality of microcontrollers at component and system level. Analyze and resolve technical issues and challenges in Fab, Probe, Assembly, Test, Application, and Design – working closely with global product, design, wafer fab process, device engineering and manufacturing teams. Support R&QA and Field Quality/Application in resolving customer applications issues. Support the development and manufacturing of highly integrated processors. Perform ATE test software programming, debugging and electrical failure analysis. Carry out test insertion reduction, parallel test conversion, test platform transfers, and development of innovative test methodologies. Perform qualification of design/process changes, wafer fab transfers, and new package release. 
     
     

    Achievement:

  • Supported multiple Teradyne platforms for test program conversion, test time reduction, yield improvement and gate failure analysis.
  • Certified Teradyne training in Tiger and Ultraflex platform.
  • Familiar with programming language, Tiger – C++ and Ultraflex – VB, revision control tool DesignSync, SVN. 
  • Test program owner of PowerQuicc III family products, integrated communication and networking microcontroller.
  • Familiar with test flow methodology, parametric and functional tests insertion such as DDR, Lynx, eTSEC, LBIU, JTAG, BIST, DFT test development.
  • On assignment at Austin, Texas for new dual core networking chip Ultraflex test program transfer.
  •  
     

    Company : Intel Microelectronics //

    Position: Component Design Engineer

    Department: Penang Design Center, Logic Architecture Verification LAV 

    Job Description:

    Responsible for the delivery of high quality VLSI design in a timely and cost effective manner. The area of responsibility covers design validation, logic verification, test plan development, design methodology development. Required to execute the design tasks with supervision and prioritize the tasks given and review decision with supervisor before implementation. Expected to be proficient with design tools and methodology and able to contribute to the project with minimum overhead. Work effectively within the project team and able to interface with supporting groups to solve problems. Take initiative to be an active participant of a team to influence the course of the project. Expected to continuously drive my professional and selfdevelopment. Excel in Intel Basics; keep the work environment safe, and role model Intel values in the course of the work. 

    Achievement:

  • years relevant experience in design and validation technique for mobile, desktop and server chipset in Intel design engineering field.
  • Familiar with industry spec such as PCIExpress, FSB, DDR protocol and possess computer language literacy such as Perl, Verilog, and  VHDL.
  • Familiar with environment setup, RTL model build flow, revision control tool RCS, CVS. Involved in RTL, FullChip and GLS Gate Level Simulation regression debug.
  • Developed test plans, multiple focus and random test cases based on architecture spec and coded functional coverage and echecks to validate functionality of designs.
  • Sole owner of flexconfig programming. PCIExpress Link Layer Regression and C/C Transaction Layer Test Plan ownership.
  • Fullchip Error Handling and ProducerConsumer Validation owner for P, G and G chipset family.
  • DMA Cluster and Fullchip event tracking owner, test development, test regression and test debug owner.
  • On assignments at Folsom, Santa Clara and Irvine, California, for DMA technology transfer and Northbridge project design engagement.
  •  

    Company : Sabah Electricity Sdn. Bhd /

    Position: Management Trainee

    Department: Protection and Communication Department

               Transmission Maintenance Department

               System Operation Department

    Job Description:

    The job primarily focus on the routine maintenance in substation, conduct testing such as Transformer Turn Ratio test, Oil Dielectric test, inspection and installation of equipment such as OLTC, insulator, power recovery after tripping etc. Learned to evaluate power load from the control room, forecast power usage and demand of the day and decision for shutting down or switC.g on transmission line from the generation side before to transmission and distribution. 
     
     
     

    EDUCATION BACKGROUND 

    –  :  Tenaga National University

    Bachelor of Electrical & Electronics Engineering Hons.

    Overall CGPA: ./., Core CGPA:  ./.

    Final Year Project: Condition Monitoring of On Load Tap Changer in power Transformer using Motor Current. 

    TECHNICAL EXPERTISE 

    Computer language literacy: C++, Perl, Verilog, VHDL, Shadow , Assembly language, Specman, Ecoding, VB, SQL, Dragon/ Chameleon/ Bus Functional Language Intel specific language, Java

    Computer literacy on specialized design tools:  Modelsim, Specman, Verdi, Maxwell, Matlab, H/PSpice

    OS platform: Window /Millenium/XP/XP Professional, Window Workstation NT, Window Terminal Server, MS DOS, AIX, RedHat, Solaris, HPUX, HPItanium and zLinux 
     

    CAREER AMBITION 

    I’m independent and having international experience that enables me to work crosssite. I'm enthusiastic in seeking new challenges in engineering field in order to contribute my utmost talent to IT/design engineering. I wish to become a principal engineer to contribute my new idea to patent filing in order to effectively bring up the technology growth of the nations. 
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     
     


    Cancel
    Not Enough Credits
    Sorry, but you don't have enough credits to download this resume.

    Purchase more credits
    Not Available
    Sorry but this resume is not available for download. Please choose another!

    Close
    Confirm Download

    Would you like to download  for 1 credit?

    You have  credits left.

    Yes No 

    Don't ask me again
    Confirm View Complete Resume

    Would you like to view  for 1 credit?

    You have  credits left.

    Yes No 

    Don't ask me again