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Paul K. Ittoopunny 

House No : , st Floor,

rd C MAIN, OMBR Layout,

Banaswadi, Bangalore

Mobile:

Email:  
 

Career Objective

To pursue a better challenging position in frontend VLSI, to enhance my career goals prosper with the winwin organization.

Professional Experience

Total Experience  : years 

Present Employer  : Sasken Communication Technologies Ltd, Bangalore

Designation  : Senior Design Engineer

Group   : Semiconductors

Responsibilities  : Design Verification of multi million gates DSP based SoC in RTL and Gate Level.

Period of Work  : July to till date.

Previous Employer/s : HCL Technologies and CDAC India ER&DCI Trivandrum

Skill Set
  • Platform   : Windows, Unix, Linux, and Sun Solaris.
  • Languages   : Verilog, VHDL, System Verilog, C, and Cx Assembly.
  • EDA Tools   : ModelSim, VCS, NCSim, Verdi, Debusy, Specman and Actel Libero IDE.
  • Configuration Mgmt    : ClearCase, CVS and Synchronicity.
  • Professional Strength
  • Gate Level Simulation Post Layout, RTL Functional Verification in module level and System level.
  • Various Mobile DSP architecture knowledge.
  • SoC/ASIC/FPGA design and verification using, Verilog, VHDL and C.
  • Achievements and Extra Curricular Activities
  • First Rank holder in Engineering Diploma in Electronics & Communication from Kerala State, exam held in April.
  • Project details  

    NightHawk Gate Level Simulation       Jun’ – Till Date

    Client  : Qualcomm India Pvt. Ltd

    Responsibility : Gate Level Verification of various mobile chip derivatives.

    Description : Highend Mobile chip having both GSM and CDMA capabilities.

    Duration  : Months

    Tools used : ModelSim, Novas Verdi, Debussy, and Synchronicity 

    WGModem IP Gate Level Simulation       Oct’ – March’

    Client  : Nokia India Pvt. Ltd

    Responsibility : Ownership of Gate Level Verification Environment creation and Enhancement, Zero Delay and Timing Simulation of latest mobile IP Chip. IP Memory integration, and System level RTL Functional verification.

    Description : Highend Mobile chip having both GSM and CDMA capabilities.

    Duration  : Months

    Tools used : ModelSim, Novas Verdi, Debussy, and Synchronicity 

    MoCA Gate Level Simulation       Jun’ – Sept’

    Client  : Conexant Systems India Pvt. Ltd

    Responsibility : Complete ownership of Gate Level Verification of MoCA chip signoff.

    Description : MoCA protocol chip for home entertainment.

    Duration  : months

    Tools used : Cadence NCVerilog, Novas Verdi, Debussy, and Synchronicity 

    MXC RTL and Gate Level Simulation      Jan’ – April’

    Client  : Freescale India Pvt. Ltd

    Responsibility : RTL and GLS verification of complex wireless DSP in module and system level using Verilog and C. Test case and task coding of different system modules and debugging.

    Description : Module and System Level verification of GSM mobile DSP.

    Duration  : Months

    Tools used : Cadence NCVerilog, Novas Verdi, Debussy, ClearCase and various customer internal tools. 

    Unified Megacell Architecture UMA.x RTL and Gate Level Simulation   Jul’ – Dec’

    Client  : Texas Instruments India Pvt. Ltd

    Responsibility : RTL and GLS verification of complex wireless DSP in module and system level using Assembly and Specman. Debugging of Cx Emulation module, Test plan development, and test case coding of different UMA derivatives and regressions.

    Description : System level verification of advanced mobile SoC.

    Duration  : Months

    Tools used : ModelSim, VCS, Specman, Cx Assembly, ClearCase and various customer internal tools. 

    Indian Cost, FPGA Functional Verification      Oct’ – Jun’

    Client  : Teradyne Inc

    Responsibility : Verification of TCIOBridge FPGA and Malabar FPGA. Test plan development, BFM coding, task coding, and test case coding.

    Description : Enhancement of Automated Test Equipment ATE with new features.

    Duration  : Months

    Tools used : Cadence NCVerilog simulator, Simvision and ClearCase

    SupervisorArbitrator FPGA, Functional Verification     Jul’ – Sep’

    Client   : Hamilton Sundstrand Inc

    Responsibility : Simulation and Verification of Supervisor Arbitrator FPGA. Test case identification and test case coding.

    Description : Power management FPGA validation of aircraft project.

    Duration  : Months

    Tools used : Cadence NCVHDL simulator and Simvision. 

    PANINI ASIC Functional Verification      Mar’ – Jun’

    Client  : Xambala Inc

    Responsibility : RTL Functional Verification of Semantic Processor ASIC. Test case identification and test case coding with the custom tool.

    Description : Semantic processor verification of M gates ASIC processor.

    Duration  : Months

    Tools used : Synopsis VCS, Simvision and ModelSim Verilog simulator

    USB Interface for Ultrasound Liquid Level Sensor ULLS    Nov’ – Feb’

    Client  : CDAC India

    Responsibility : Firmware development of USB interfacing for an indigenous Embedded System ULLS Detail designing, development of hardware and software, Proto development, testing and implementation.

    Description : This project is a highly miniaturized Embedded System based on Texas MSP and PIC Controller for USB of PICC. The system aims a miniature board solution for the whole assembly with USB interface with external PC. The subassemblies include Echosounder based transmitter and receiver, LCD interfacing, and Keyboard interfacing.

    Duration  : months

    Tools used : MP Lab IDE

    Embedded Fish Finder with GPS Navigation FFGPS Mk III    Jan’ – Oct’

    Client  : CDAC India

    Responsibility : Detail designing, development of hardware and software, Proto development, testing and implementation.

    Description : This project is a highly miniaturized Embedded System based on Texas DSP TMSF and Actel ProASIC FPGA. The system aims a single board solution for the whole assembly with miniaturized size. The subassemblies include Echosounder based transmitter and receiver, Colour LCD interfacing, GPS interfacing, Keyboard interfacing and Thermal Printer interfacing.

    Duration  : months

    Tools used : TI Code Composer Studio for x devices, Actel Libero IDE Platinum.

    Professional and Educational Qualifications  
  • Bachelor’s Degree BE in Electronics & Communication Engineering from St. Michael College of Engineering & Technology, Sivagangai under Madurai Kamaraj University, Madurai, Tamilnadu passed with First Class .% marks aggregate in April .
  •  
  • Engineering Diploma in Electronics & Communication Engineering from Govt. Polytechnic Kunnamkulam, under Dept. of Technical Education Kerala, passed with First Rank & First Class with Distinction .% marks Aggregate in April .
  •  
  • Technical High School Leaving Certificate THSLC from Govt. Technical High School Kunnamkulam, under Dept. of Technical Education Kerala, passed with First Class .% marks Aggregate in March .
  • Personal Details
  • Date of Birth  : th May .
  • Sex   : Male.
  • Marital Status  : Married.
  • Father’s Name  : Ittoopunny K.P.
  • Religion & Caste : Christian, Orthodox.
  • Nationality  : Indian.
  • Languages Known : Malayalam and English
  • Passport Details : E.
  • Nasscom NSR ID : .
  • Permanent Address :  Paul K I
  • K. House, Santhinagar,

    Kunnamkulam,

    Thrissur District, Kerala,

    Pincode:

    Tel: , Mobile: + 


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