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<pre>Array ( [var] => cut_url ) </pre> Resume for Sriram G. for Designer / Artist / Creative / Electronics in Tampere, Finland. Search More Resumes for Designer / Artist / Creative on Resumark.com #RTSEKNXZ1
 

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Resume for Sriram G. for Designer / Artist / Creative / Electronics in Tampere, Finland




Occupation: Designer / Artist / Creative Industry: Electronics
Country: Finland City: Tampere
State: Western Finland ZIP: 33720



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Sriram G
Näytellijänkatu E
Ph:
Tampere
SUMMARY
Six years of experience as a Design and Verification engineer includes
VHDL coding, Verification and Evaluation for the systems in Telecom domain, Security domain,
Automation domain, Mechanical systems domain in FPGA’s and Specman coding for Verification, bug
detection in Telecom domain.
Embedded design, Systemon Chip SOC Design
Hardware testing through JTAG emulator, logic analyzer and protocol analyzer.
SPECIALITIES
Development – Concept, design, test, software integration, validation, release and support
Managed a small team in the projects
Embedded design with CMMi level and ISO process adherence
Contribution for process and quality in the domain level
WORK EXPERIENCE
Design Engineer Etteplan Oyj, September Till date
Worked on design, RTL development, toplevel integration and evaluation of various interfaces for
automation industry and documenting the same. Development of Intellectual property designs and
involved in ISO process development. Significant works are below:
Design and development of algorithm for Demodulator and other logic interfaces.
Integration and development of various modules of the resolver interface.
Development of SPI and SD card controller protocol
Senior Design Engineer, GDA Technologies, India, / – /
Design, RTL development, toplevel integration, testbench development and evaluation. Development of
verification& testing plan, verification environment using System Verilog. Involved in the CMMi level
process development for ASIC frontend and FPGA domain and ISO auditing and the works are
below:
Design of algorithm for Camera, DDR, LCD module, ADC module interfaces for surveillance systems.
HDMI video and audio interfaces
Design Engineer, Wipro Technologies, India, / – /Three Projects
Developed the verification environment, verification interfaces, functional coverage monitors, protocol
monitors, and testcases for the codec block using Specman in telecom domain. Created the verification
plan and test plan for the CODEC projects. Developed the filter module for CODEC in Matlab and cross
verified with the design under test module.
Project Engineer, Xalted Networks, India, / – /
HDL Implementation and Documented the implementation of Multiple Channel SONET/SDH Overhead
Processing for SONET/SDH Transport Network.
Research Assistant, Regional Engineering College NIT, India, / – /
Coordinator of the certificate course run by the college. HDL implementation and documentation for the
works below:
Developed FPGA based highfrequency digital signals using DDFS and CORDIC method.
Developed a FAST and AREA concise multiplier
Development of interfacing between TMSCx DSP with Altera FPGA
Implementation of ITUT G. standard in FPGA
Implementation of wavepipelined FIR Filter in SPARTAN FPGA
EDUCATION
M.Tech, VLSI Design
SRM University,
M.Sc,
Electronics
Bharathidasan University,
B.Sc
Industrial Electronics Bharathidasan University,
TECHNICAL PRESENTATIONS
. Design and FPGA Implementation of Image Block Encoders with DDWT, IEEE TENCON
. Design and Implementation of FPGA based Fast Multipliers with Optimum Placement and Routing
using Structure Organizer, National conference on VLSI Testing
TECHNICAL EXPERIENCE
HDL
: VHDL, Verilog
PROGRAMMING LANGUAGE
: C, C++
PROTOCOL
: PCM, IS, TDM, SPI
VERIFICATION LANGUAGE
: Specman, System Verilog
FPGA TOOLS
: Xilinx ISE, Altera MAXPLUS II, Altera Quartus II
SIMULATION
: Modelsim, NCSim, Debussy
SYNTHESIS
: Leonardo Spectrum, Precision Synthesis, XST, Quartus II
VERSION CONTROL
: Clearcase
Operating System
: MSWindows, Linux, Solaris

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