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S. Maison de Champréveyres N, Rue de la Dîme, CH Neuchâtel Mobile No: + Email: ,
/ / Msc Major MicroElectronics Ecole Polytechnique Fédérale de Lausanne GPA : ./ Lausanne, Switzerland
/ / Birla Institute of Technology & Science Pilani B.E.Hons in Electrical & Electronics M.Sc.Hons in Mathematics CGPA : ./ / Percentage: .% th StandardJammu & Kashmir State Board, J&K
* Worked as Master Thesis intern in CSEMSA, Switzerland for duration of months. * Worked as an intern in Freescale semiconductor India Pvt Ltd Noida, UP for a period of months.
MASTER THESIS PROJECT
/ / CSEM SA Neuchatel,Switzerland Title of the Project: Pixel noise analysis for high dynamic range low noise performance of vision sensor. Details: The goal of this project was do rigorous noise analysis of existing pixel circuit which is used in vision sensor in order to estimate the performance of sensor and to investigate new solutions suited for machine vision applications in uncontrolled environment, featuring both a very high intrascene dynamic range and a very low noise to extend their operability in dark environments. I worked in a team of people at CSEMSA for this project and was successful in completing this project in the duration of months. I will also publish a research paper on the work which I did during my master thesis along with my supervisor and coadvisors at the company.
/ / EPFL, RFIC Group Switzerland Title of the Project: Design of a Voltage Reference circuit for a Comparator used in Remotely Powered Biosensor Systems. Details: The main objective of my Project is to design a lowPower consumption Voltage Reference circuit which produces a Reference Voltage independent of Power Supply and Temperature. Different Topologies for designing the Comparator and Voltage Reference circuit are compared and analyzed. Designed Voltage Reference was used in the power sensing circuit of the implanted device to monitor the amount of power received by the implant which was useful for the project of PhD students.
/ / EPFL, Lausanne Switzerland Project Title: Viterbi ACS Semicustom and Fullcustom Design Details: The Project aims at implementing Viterbi ACS unit using semicustom approach with the design working at minimum speed of MHz and full custom design for .GHz . Adder and Comparator blocks of Viterbi ACS are designed using the full custom approach to achieve maximum speed.
/ / Freescale Semiconductors,R&D Center Noida, India
Project Title: Layouts using Virtuoso XL Layout Editor, USB PHY . Squelch Detection Circuit & Simulations. Details: . USB .: Simulating and analyzing the behaviour of USB High Speed transmitter in High Speed Host & Device Mode using Ultrasim as a Fast Chip Spice Simulator. . Analog & Digital Layouts using VXL: Automating the process of layout making by exploring Virtuoso XL Layout editor features was done in nm, nm, soi CMOS Technologies. Various techniques for Analog Layouts like common Centroid, Multi gate finger layout, minimising series resistance in digital circuits using for good switching speeds, etc were followed to design layouts.
Central Electronics Engineering Research Institute
Project Title: Gate Sensitization Materials for Fabricating Chemical & Sensors using ISFET Ion Sensitive Field Effect Transistor. Details: Different journals and research papers were read in order to investigate the gate sensitization materials used in the membrane for the detection of a particular type of ion using ISFET.
TECHNICAL EXPERIENCE Programming Languages: VHDL,C, Verilog ,VHDLAMS. Tools Used: Cadence, Eldo, Modelsim, Synopsys, Encounter, Mathematica, Micro wind, Xilinx, TetraMax,AutoCAD. ACHIEVEMENT/AWARDS/EXTRACURRICULAR ACTIVITIES
· · · · · Secured th Rank in my StateJammu and Kashmir,India during my Th Standard. Secured many awards at State Level Painting competitions. Active Participant in cultural activities Dance,Fashion show during my Bachelor studies at BITS,Pilani. Secured prizes for participation in various sports and cultural activities during my school. Secured merit scholarship from my education institute for best performance during my studies.