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<pre>Array ( [var] => cut_url ) </pre> Resume for Oleg S. for Engineer / Electronics in Moscow, Russian Federation. Search More Resumes for Engineer on Resumark.com #U3APBRKLB
 

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Resume for Oleg S. for Engineer / Electronics in Moscow, Russian Federation




Occupation: Engineer Industry: Electronics
Country: Russian Federation City: Moscow
State: Moscow City ZIP: 124498



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RESUME 

  • OBJECTIVE
  • ESD / Reliability & Quality / Product Engineer / CMOS Device Eng.

  • PERSONAL INFORMATION
  • Full Names: Dr. Oleg S.

    Citizenship: Canadian

    Address: Building , Apt. , Zelenograd, Moscow, Russia

    Email:

    Phone: home 

  • EDUCATION
  • M.A.Sc. in Electrical Engineering May Aug. University of Waterloo, Canada. The thesis title is "Impact of Technology Scaling on Bridging Fault Modeling and Detection in CMOS Circuits."

    Ph.D. in Microelectronics Technology May Oct. – Moscow University of Electronics and Technology, Russia. The thesis title is "Investigation and Development of "SilicononInsulator" structures using a selective chemical etching of silicon."

    Engineer Degree Sept. March Moscow University of Electronics and Technology, Russia.  

  • EMPLOYMENT EXPERIENCE
  • Senior I/O ESD Development & Reliability Engineer Sept. – Present – Freescale Semiconductor, Research Lab, Moscow, Russia

    Research Assistant Professor Oct. – June University of Waterloo, E&CE Department, Canada

    PostDoctoral Fellow Sept. Sept. University of Waterloo, E&CE Department, Canada

    Teaching Assistant Sept. April University of Waterloo, Canada.

    Senior Process Engineer Nov. May JSC «Korona Semiconductor», Moscow, Russia

    Research Engineer May Sept. Moscow Institute of Electronic Technology Technical University, Moscow, Russia 

  • RESEARCH EXPERIENCE
  • Reliability, quality and scaling issues of CMOS devices/ICs

    Burnin testing and ESD design of submicron ICs

    Thermal management/selfheating of VLSIs

    Design and physical modeling of power SOI MOSFETs

    Chemical wet etching of silicon

    Glasslike insulators for silicononinsulator SOI structures  

  • TEACHING EXPERIENCE
  • Lecturer for the "Electronic and Electrical Properties of Materials" undergraduate course ~ students, tutorials, midterm and final exams

    Teaching Assistant for the "Digital Integrated Circuits" undergraduate course ~ students, tutorials, labs

    Teaching Assistant for the "Electronic Devices" undergraduate course ~ students, tutorials, labs   

  • TECHNICAL EXPERTISE
  • VLSI and ESD design tools Cadence, HSPICE, Spectre, Sequoia

    Device simulation tools D Microtec, Medici

    Yield enhancement tool Sequoia Cell Designer

    ESD testers TLP system and HBM/MM testers. 

  • AWARDS & SCHOLARSHIPS
  • Faculty of Engineering Scholarship, University of Waterloo

    Ontario Graduate Scholarship

    Graduate Scholarship of Moscow Government 

  • REFERENCES
  • Prof. M. Sachdev, University of Waterloo, E&CE Department, Canada

    Dr. M. Obrecht, Siborg Corp., Canada

    Dr. A. Vassighi, Senior Quality Engineer, Intel Corporation, OR, USA

    Prof. A. Kaltchenko, Physics & Computer Science Department, Wilfrid Laurier University, Canada

    SELECTED PUBLICATIONS

    Books

  • O. S., H. Sarbishaei and M. Sachdev, "CMOS Devices and Circuit Design for ESD Protection," published by Springer Publisher, May .
  •  

    Journal papers

  • O. S. and S. Somov, ″ESD protection design for I/O libraries in advanced CMOS technologies,″ SolidState Electronics journal, vol. , p. , .
  • O. S., A. Kaltchenko, "Temperature Dependence of IDDQ Distribution: Application for Delta IDDQ Testing," accepted for publication in IET Circuits, Devices & Systems journal, Sept. .
  • O. S., A. Vassighi, and M. Sachdev, "Impact of selfheating effect on longterm reliability and performance degradation in CMOS circuits," EEE Trans. on Device and Materials Reliability journal, vol. , No. , p. , .
  • O. S., H. Sarbishaei, V. Axelrad, and M. Sachdev, "Novel gate and substrate triggering techniques for deep submicron ESD protection devices," Microelectronics Journal, vol. , p., .
  • O. S., M. Obrecht and M. Sachdev, "Evaluation of STI degradation using temperature dependence of leakage current in parasitic STI MOSFET," Microelectronics Reliability journal, vol. , No. , p. , .
  • O. S., H. Sarbishaei, V. Axelrad and M. Sachdev, "The impact of CMOS technology scaling on MOSFETs second breakdown: Evaluation of ESD robustness," Microelectronics Reliability journal, vol. , No. , p. , .
  • A. Vassighi, O. S., M. Sachdev, A. Keshavarzi and C. Hawkins, "CMOS IC technology scaling and its impact on burnin Invited paper" IEEE Trans. on Device and Materials Reliability, vol. , No., p. , .
  • O. S., A. Vassighi, M. Sachdev, A. Keshavarzi and C.F. Hawkins, "Effect of CMOS technology scaling on thermal management during burnin," IEEE Transactions on Semiconductor Manufacturing, vol. , No. , p. , Nov. .
  • O. S., A. Vassighi and M. Sachdev, "Impact of technology scaling on thermal behavior of leakage current in subquarter micron MOSFETs: Perspective of low temperature current testing," Microelectronics Journal, vol. , No. , p. , .
  • O. S., A. Vassighi and M. Sachdev, "Leakage current in subquarter micron MOSFET: A perspective on stressed delta IDDQ testing," Journal of Electronic Testing JETTA, vol. , No., pp. , .
  • O. S., A. Pradzinski and M. Sachdev, "Impact of Gate Induced Drain Leakage on overall leakage of submicron CMOS VLSI Circuits," IEEE Transactions on Semiconductor Manufacturing, vol., No. , p. , Feb. .
  • N. Koshelev, O. S. and A. Ermolaeva, "Glasslike dielectrics for bond and etch back silicononinsulator BESOI technology," Journal of Advanced Materials, No. , p., . 
  • O. S., V. Petrova and N. Koshelev, "Silicononinsulator structures formation using the selective chemical etching," Journal of Electronic Industry, No , p. , in Russian.
  • O. S., G. Vasiliyev and K. Barinov, "Diffusion system for diffusion layer formation in large diameter silicon wafers," Journal of Electronic Industry, No , p. , in Russian.
  •  

    Conference papers

  • H. Sarbishaei, O. S., and M. Sachdev, "A transient power supply ESD clamp with CMOS thyristor delay element," EOS/ESD Symposium, p. A., Sept. .
  • H. Sarbishaei, O. S., and M. Sachdev, "Optimizing Circuit Performance and ESD Protection for HighSpeed Differential I/Os," Custom Integrated Circuits Conference CICC, p. , .
  • O. S., H. Sarbishaei and M. Sachdev, "Analysis and design of LVTSCRbased EOS/ESD protection circuits for burnin environment," IEEE Int. Symp. on Quality of Electronic Design ISQED, p. , .
  • A. Vassighi, O. S. and M. Sachdev, "Thermal runaway avoidance during burnin," Int. Reliability Phys. Symp. IRPS, p. , .
  • A. Vassighi, O. S., M. Sachdev and A. Keshavarzi, "Power management of deep submicron technologies in burnin environment," IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems DFT', Cambridge, MA, USA, p. , Nov. .
  • O. S., A. Vassighi, M. Sachdev, A. Keshavarzi and C.F. Hawkins, "Burnin temperature projections for deep submicron technologies," IEEE Int. Test Conference, p. , Oct. .
  • O. S., A. Pavlov, and M. Sachdev, "Subquarter micron SRAM cells stability in lowvoltage operation: A comparative analysis," IEEE Int. Integrated Reliability Workshop IRW, p. , Oct. .
  • A. Vassighi, O. S., M. Sachdev and A. Keshavarzi, "Effect of static power dissipation in burnin environment on yield of VLSI," IEEE Int. Symposium on Defect and Fault Tolerance in VLSI Systems DFT', Vancouver, Canada, p. , Nov. .
  • A. Vassighi, O. S., M. Sachdev and A. Keshavarzi, "Impact of power dissipation on burnin test environment for submicron technologies," IEEE Int. Workshop on Yield Optimization and Test YOT, Oct. . 
  • O. S., B. Chatterjee and M. Sachdev, "Impact of technology scaling on bridging fault modeling in CMOS circuits," IEEE Int. Workshop on Defect Based Testing DBT, p. , April .
  • O. S., A. Pradzinski and M. Sachdev, "Contribution of Gate Induced Drain Leakage to overall leakage and yield loss in digital submicron VLSI Circuits," IEEE Int. Integrated Reliability Workshop IRW, p. , Oct. .
  • O. S. and M. Sachdev, "Impact of technology scaling on bridging fault detections in sequential and combinational CMOS circuits," IEEE Int. Workshop on Defect Based Testing DBT, p. , April .
  • O. S. and M. Sachdev, "Impact of technology scaling on bridging fault detections," IEEE Canadian Conference on Electrical and Computer Engineering, p. , March .
  •  
     
     

    The Detailed Information about Employment/Research Experience

  • Senior I/O ESD Development Engineer July – Present
  • ESD protection/integration of I/O cells, TLP and HBM/MM measurements, latch up issues, device and ICs reliability burnin, oxide breakdown and electromigration in nm and nm CMOS/SOI and SMARTMOS technologies. I am working with internal Freescale customers from wireless, networking and automotive business groups located in Arizona and Texas. In addition, my obligations include the scheduling, project tracking and quality audit of I/O libraries.

  • Research Assistant Professor/ PostDoctoral Fellow Sept. June
  • ESD design and optimization for highperformance CMOS ICs the impact of CMOS technology scaling on ESD gategrounded NMOSFET, LVTSCR robustness. ESD testing using TLP, HBM and MM test techniques. This is the research project with Gennum Corp., Canada.

    the impact of CMOS technology scaling on reliability/quality and testing of submicron devices and CMOS ICs for example, the effect of CMOS process variations on reliability and robustness of sub. um embedded SRAM cells. This is the research project with Philips Res. Lab., The Netherlands.

    the optimization of current/logic and burnin testing for high leaky CMOS technologies for example, the estimation of effectiveness of bridging faults and gate oxide shorts detection in scaled down ISCAS/ benchmark circuits using current/logic testing   

    the yield loss, thermal management and thermal run away issues of burnin testing for example, the optimization of burnin conditions stress temperature and voltage for highperformance circuits, such as microprocessors This is the research project with Intel Microprocessor Res. Lab., USA.

    the device and circuit design for reliability/quality and the analysis of leakage current components in subquarter micron CMOS technologies for example, the layout optimization for gate induced drain leakage current reduction in deep submicron digital CMOS ICs.   

  • Senior Process Engineer Nov. May
  • The JSC "Korona Semiconductor» Moscow has the CMOS product line for . um and . um technologies. During two years, I worked in this company as a senior process engineer. My main obligations were to control the wet etching and cleaning of silicon wafers between CMOS technology steps using laminar flow wet benches and to manage the wet etching of aluminum metallization using PAN etch solution of HPO:DIHO:HNO:CHCOOH. Other process operation, where I worked, was the Spinon Glass SOG Planarization. At this technology step we used the SOG equipment from Secon Semiconductor Equipment GmbH, Austria and SOG solutions from Allied Signal, Inc. and Filmtronics, Inc. The different failure analysis methods were used to yield enhancement during etching and SOG planarization technology steps.

  • Research Engineer May

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