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<pre>Array ( [var] => cut_url ) </pre> Resume for Arshak A. for Manager / Supervisor / Team Leader / Electronics in Yerevan, Armenia. Search More Resumes for Manager / Supervisor / Team Leader on Resumark.com #R482IHIFA
 

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Resume for Arshak A. for Manager / Supervisor / Team Leader / Electronics in Yerevan, Armenia




Occupation: Manager / Supervisor / Team Leader Industry: Electronics
Country: Armenia City: Yerevan
State: Yerevan ZIP: 0034



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Arshak A.

Andraniki st, apt , Yerevan, Armenia ▪ Phone: ▪

OBJECTIVE

Seeking a challenging position in ASIC Design and/or Verification area, where my skills and experience will greatly enhance the company's success and my personal growth.

HIGHLIGHT OF SKILLS AND QUALIFICATIONS
  • Over years of work experience involving management and supervisory role
  • Possess strong administration and organizational skills
  • Skilled at problem solving
  • Resourceful with sound judgement and initiative
  • Able to work very well independently, as a team member and  as a team leader
  • Excellent multitasking skills with ability to plan and prioritize important tasks
  • Organized with great attention to details, professional, dedicated and reliable
  • Technical skills: RTL design, Memory BIST, Verilog/VHDL, TCL, NCVerilog, Model Sim, VCS, SpyGlass, Unix, Linux, Windows
  • PROFESSIONAL EXPERIENCE VIRAGE LOGIC CORPORATION / Present

    Manager, RTL Design  / Present 

    Manage a staff of engineers

    Responsible for design of new architecture, development of compiler, RTL, testbench and technical documentation.

    Participated in development of a standard describing memories SRAM and ROM under test a USA patent is pending.

    Received company award for design of BIST/BIRA compiler for AMD nm SOI SRAM memories.

    Received company award for organizing and leading incompany internship trainings.

    Senior Engineer, RTL Design  / /

    Supervised a staff of engineers.

    Development and functional verification of Memory BIST/BIRA compilers for Virage Logic memories.

    Customer support.

    Engineer, RTL Design / /

    Development and functional verification of Memory BIST/BIRA compilers for Virage Logic memories.

    Customer support.

    EPYGI LLC / /

    Design Engineer

    Developed Verilogbased FFT Fast Fourier Transform and convolutional interleaver for Altera's FPGAs.

    Scientific Research Institute of Computers Engineering  / / Hardware Design Engineer 

    Developed devices for remote control, information gathering and processing.

    Developed software for Altera's and controllers.

    OTHER ACTIVITIES Yerevan State University  / 

    Memory Test and Repair Lecturer Gyumri Information Technologies Training Centre  / / 

    Digital Design Lecturer, Verilog HDL Lecturer  EDUCATION

    Yerevan State University, Yerevan, Armenia  / / 

    MS in Radiophysics and electronics,                                      

    Diploma with Honor 

    Participated in the following management trainings: / /

    Creative Leadership

    Conflict Management

    Performance Evaluation

    Change Management

    References Available Upon Request

    Arshak A.

    Andraniki st, apt , Yerevan, Armenia ▪ Phone: ▪

    OBJECTIVE

    Seeking a challenging position in ASIC Design and/or Verification area, where my skills and experience will greatly enhance the company's success and my personal growth.

    HIGHLIGHT OF SKILLS AND QUALIFICATIONS
  • Over years of work experience involving management and supervisory role
  • Possess strong administration and organizational skills
  • Skilled at problem solving
  • Resourceful with sound judgement and initiative
  • Able to work very well independently, as a team member and  as a team leader
  • Excellent multitasking skills with ability to plan and prioritize important tasks
  • Organized with great attention to details, professional, dedicated and reliable
  • Technical skills: RTL design, Memory BIST, Verilog/VHDL, TCL, NCVerilog, Model Sim, VCS, SpyGlass, Unix, Linux, Windows
  • PROFESSIONAL EXPERIENCE VIRAGE LOGIC CORPORATION / Present

    Manager, RTL Design  / Present 

    Manage a staff of engineers

    Responsible for design of new architecture, development of compiler, RTL, testbench and technical documentation.

    Participated in development of a standard describing memories SRAM and ROM under test a USA patent is pending.

    Received company award for design of BIST/BIRA compiler for AMD nm SOI SRAM memories.

    Received company award for organizing and leading incompany internship trainings.

    Senior Engineer, RTL Design  / /

    Supervised a staff of engineers.

    Development and functional verification of Memory BIST/BIRA compilers for Virage Logic memories.

    Customer support.

    Engineer, RTL Design / /

    Development and functional verification of Memory BIST/BIRA compilers for Virage Logic memories.

    Customer support.

    EPYGI LLC / /

    Design Engineer

    Developed Verilogbased FFT Fast Fourier Transform and convolutional interleaver for Altera's FPGAs.

    Scientific Research Institute of Computers Engineering  / / Hardware Design Engineer 

    Developed devices for remote control, information gathering and processing.

    Developed software for Altera's and controllers.

    OTHER ACTIVITIES Yerevan State University  / 

    Memory Test and Repair Lecturer  
    Gyumri Information Technologies Training Centre  / / 

    Digital Design Lecturer, Verilog HDL Lecturer  EDUCATION

    Yerevan State University, Yerevan, Armenia  / / 

    MS in Radiophysics and electronics,                                      

    Diploma with Honor 

    Participated in the following management trainings: / /

    Creative Leadership

    Conflict Management

    Performance Evaluation

    Change Management

    References Available Upon Request


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