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<pre>Array ( [var] => cut_url ) </pre> Resume for Dong J. for Researcher / Scientist / Electronics in Minneapolis, Minnesota. Search More Resumes for Researcher / Scientist on #T2XTZLBXW

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Resume for Dong J. for Researcher / Scientist / Electronics in Minneapolis, Minnesota

Occupation: Researcher / Scientist Industry: Electronics
Country: United States City: Minneapolis
State: Minnesota ZIP: 55414

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Dong J.

Union Street SE                                                 

Minneapolis, MN,                                              


   An internship position in the area of VLSI design


  • – Present  Ph.D. expected in  University of Minnesota, Twin Cities
  •    Electrical & Computer Engineering GPA ./.

  • –    B.E. with Honor Tsinghua University, Beijing, China
  • Electrical Engineering GPA /, Rank: out of

    Research Experience                                   

    Aug. – present    VLSI Design Group   University of Minnesota
  • Multiple fullcustom tapeout experience using nm technology. Designs include PLLs, differential VCOs, pseudorandom binary sequence generators, clock distributions network, scan in/out control circuits, noise sensors, etc.
  • Fullcustom tapeout experience using nm DIC technology to implement a k SRAM. Designs include memory cells, row/column decoders, sense amplifiers, control signal generators, etc.
  • Jun. – Aug.    Memory Design Group   Seagate LLC, MN
  • Row decoder design and simulation for M MRAM.
  • Functional simulation and analysis on k MRAM design.
  • Aug. – Jul.    Analog CAD Group   University of Minnesota
  • Applied modelorder reduction technique on a biological problem, model of yeast pheromone pathway. A paper on this topic was accepted by ICCAD.
  • Finished a device model compiler for a Matlabbased circuit simulator. The compiler could be used to integrate VerilogA device models into that simulator.
  • Spring    “Analog Circuits for Wireless Comm.” University of Minnesota
  • To design major components of a direct conversion receiver including a differential LNA, an IO mixer and a low pass filter.
  • Spring     “VLSI Design Laboratory”   University of Minnesota
  • Implemented parallel LDPC encoder and decoder using Verilog.
  • Fall – Spring  “Digital IC Design I, II”    University of Minnesota
  • Schematic and layout design of a bit carry lookahead adder.
  • Schematic and layout design of a k SRAM.
  • Fall     “Analog IC Design”     University of Minnesota
  • Finished both schematic and layout design of a second order SigmaDelta AD converter. Design of an ultra low power OTA is also included.


  • Design Tools:  Cadence, HSPICE, NANOSIM, HSIM, Verilog, VHDL, VCS, DC
  • Programming:  C/C++, Perl, Matlab

    PUBLICATIONS & PATENTS                                           

  • D. J., J. Gu and C. H. Kim, “Circuit Techniques for Enhancing the Clock Data Compensation Effect under Resonant Supply Noise”, Custom Integrated Circuits Conference CICC, Sep. .
  • D. J., J. Gu, P. Jain and C. H. Kim, "Enhancing Beneficial Jitter Using PhaseShifted Clock Distribution", International Symposium on Low Power Electronics and Design ISLPED, Aug. .
  • D. J., J. Gu and C. H. Kim, “Circuit Design and Modeling for Enhancing the Clock Data Compensation Effect under Resonant Supply Noise, submitted to IEEE Journal of SolidState Circuits JSSC.
  • D. J., H. Li, R. Wang, H. Huang and Y. Chen, "Integrated Circuit Active Power Supply Regulation", U.S. Patent, pending, /,.

    SELECTED HONORS                                     

  •  ECE Department Research Fellowship, University of Minnesota
  •   Honor Graduates of Tsinghua University, Beijing, China
  •     out of students

  •    Consecutive First Class Fellowship of Tsinghua University, Beijing, China
  •     out of students 


  • Dr. Chris Kim  Associate Professor, ECE Department, University of Minnesota
  • Union St SE, Minneapolis, MN ,

  • Dr. Yiran Chen Staff Engineer, Seagate Technology
  • Computer Ave, Bloomington, MN ,

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