RTL Design and Development of Cryptography macrocells in Smartcard products
o Designed and Developed AES Standard for bit platform in VHDL for brand protection
o Verified EDES Encryption Standard in Clanguage for Smartcard product.
Development of assertion checkers and coverage analysis
o Created assertions in Property Specification Language PSL for EDES and AES macrocell
to run along with the design under test
o Developed Coverage cells for the Design and analyzed the holes in coverage and fixing
Creation of constrainedrandom verification environment in Specman for Single Wire
o Developed the verification environment for SWP Protocol model using Specman compliant
to eRM standards.
o Developed sequence library to perform constrained on the fly generation of seeds for several
o Developed checkers and monitors to track changes on the DUT and compare with the model
in the scoreboard in realtime.
o Built the environment as a selfchecking model and created test cases to verify the DUT
with best possible coverage.
Creation of constrainedrandom complete verification environment in Specman for AES
o Successfully created an interface between AES Specman environment and Clanguage data
o Created AES Verification Environment on bit platform for brand protection application
o Developed selfchecking model for verification of critical functionality and created test
scenarios for to verify with % functionality coverage